Efficient logic circuit for network intrusion detection

Huang Chun Roan, Chien Min Ou, Wen Jyi Hwang*, Chia Tien Dan Lo

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

4 引文 斯高帕斯(Scopus)

摘要

A novel architecture for a hardware-based network intrusion detection system (NIDS) is presented in this paper. The system adopts an FPGA-based signature match co-processor as a core for the NIDS. The signature matcher is based on an algorithm that employs simple shift registers, or-gates, and ROMs in which patterns are stored. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of network intrusion detection.

原文英語
主出版物標題Embedded and Ubiquitous Computing - International Conference, EUC 2006, Proceedings
發行者Springer Verlag
頁面776-784
頁數9
ISBN(列印)3540366792, 9783540366799
出版狀態已發佈 - 2006 一月 1
事件International Conference on Embedded and Ubiquitous Computing, EUC 2006 - Seoul, 大韓民國
持續時間: 2006 八月 12006 八月 4

出版系列

名字Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
4096 LNCS
ISSN(列印)0302-9743
ISSN(電子)1611-3349

其他

其他International Conference on Embedded and Ubiquitous Computing, EUC 2006
國家/地區大韓民國
城市Seoul
期間2006/08/012006/08/04

ASJC Scopus subject areas

  • 理論電腦科學
  • 電腦科學(全部)

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