Efficient K-means VLSI architecture for vector quantization

Hui Ya Li*, Wen Jyi Hwang, Chih Chieh Hsu, Chia Lung Hung

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

1 引文 斯高帕斯(Scopus)

摘要

A novel hardware architecture for k-means clustering is presented in this paper. Our architecture is fully pipelined for both the partitioning and centroid computation operations so that multiple training vectors can be concurrently processed. The proposed architecture is used as a hardware accelerator for a softcore NIOS CPU implemented on a FPGA device for physical performance measurement. Numerical results reveal that our design is an effective solution with low area cost and high computation performance for k-means design.

原文英語
主出版物標題Image Analysis - 16th Scandinavian Conference, SCIA 2009, Proceedings
頁面440-449
頁數10
DOIs
出版狀態已發佈 - 2009
事件16th Scandinavian Conference on Image Analysis, SCIA 2009 - Oslo, 挪威
持續時間: 2009 六月 152009 六月 18

出版系列

名字Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
5575 LNCS
ISSN(列印)0302-9743
ISSN(電子)1611-3349

其他

其他16th Scandinavian Conference on Image Analysis, SCIA 2009
國家/地區挪威
城市Oslo
期間2009/06/152009/06/18

ASJC Scopus subject areas

  • 理論電腦科學
  • 電腦科學(全部)

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