Efficient header classification architecture for network intrusion detection

Wen-Jyi Hwang, Chien Min Ou

研究成果: 雜誌貢獻文章


In this paper, an efficient FPGA-based header classification circuit is proposed for network intrusion detection system (NIDS). The circuit is based on simple shift registers and symbol encoders for the fast packet header classification in hardware. As compared with related work, experimental results show that the proposed work achieves higher throughput and less hardware resource in the FPGA implementations of NIDS systems.

頁(從 - 到)1839-1853
期刊Journal of Information Science and Engineering
出版狀態已發佈 - 2009 十一月 1

ASJC Scopus subject areas

  • Software
  • Human-Computer Interaction
  • Hardware and Architecture
  • Library and Information Sciences
  • Computational Theory and Mathematics

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