Efficient hardware architecture based on generalized Hebbian algorithm for texture classification

Shiow Jyu Lin, Yi Tsan Hung, Wen Jyi Hwang

研究成果: 雜誌貢獻文章同行評審

6 引文 斯高帕斯(Scopus)

摘要

The objective of this paper is to present an efficient hardware architecture for generalized Hebbian algorithm (GHA). In the architecture, the principal component computation and weight vector updating of the GHA are operated in parallel, so that the throughput of the circuit can be significantly enhanced. In addition, the weight vector updating process is separated into a number of stages for lowering area costs and increasing computational speed. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is designed. It is embedded in a system-on-programmable-chip (SOPC) platform for physical performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs.

原文英語
頁(從 - 到)3248-3256
頁數9
期刊Neurocomputing
74
發行號17
DOIs
出版狀態已發佈 - 2011 十月 1

ASJC Scopus subject areas

  • Computer Science Applications
  • Cognitive Neuroscience
  • Artificial Intelligence

指紋 深入研究「Efficient hardware architecture based on generalized Hebbian algorithm for texture classification」主題。共同形成了獨特的指紋。

引用此