Efficient architecture for island genetic algorithm in reconfigurable hardware

A novel VLSI architecture for an island genetic algorithm (GA) is presented in this paper. The island GA is based on steady-state GA for reducing the hardware resources consumption. Alook-up table based fast string migration architecture is proposed for lowering the computational overhead while enhancing the performance for the island GA. As compared with its single-island GA hardware counterpart, the proposed architecture attains superior performance with less computation time subject to the same total population size. In addition, the proposed architecture has significantly lower computational time as compared with its software counterparts running on cluster computer with multithreading for GA-based optimization.