Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays

Chang Chun Lee, Chuan Hsi Liu, Dian Yong Li, Chia Ping Hsieh

研究成果: 雜誌貢獻文章

摘要

The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

原文英語
頁(從 - 到)230-234
頁數5
期刊Microelectronics Reliability
83
DOIs
出版狀態已發佈 - 2018 四月 1

指紋

dummies
Transistors
transistors
mechanical properties
Mechanical properties
n-type semiconductors
MOSFET devices
silicon
Silicon
metal oxide semiconductors
layouts
isolation
field effect transistors
engineering
simulation

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Safety, Risk, Reliability and Quality
  • Surfaces, Coatings and Films
  • Electrical and Electronic Engineering

引用此文

Effect of contact-etch-stop-layer and Si1-xGex channel mechanical properties on nano-scaled short channel NMOSFETs with dummy gate arrays. / Lee, Chang Chun; Liu, Chuan Hsi; Li, Dian Yong; Hsieh, Chia Ping.

於: Microelectronics Reliability, 卷 83, 01.04.2018, p. 230-234.

研究成果: 雜誌貢獻文章

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abstract = "The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40{\%} higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.",
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AU - Lee, Chang Chun

AU - Liu, Chuan Hsi

AU - Li, Dian Yong

AU - Hsieh, Chia Ping

PY - 2018/4/1

Y1 - 2018/4/1

N2 - The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

AB - The layout effect influences the performance of nanoscale devices with advanced strain engineering, considering that the size of a technology node continuously shrinks to ≤ 20 nm. Transistors with a long gate width could be fabricated, and the portion that protrudes outside the channel region could be located on a soft shallow trench isolation region and even across the dummy active region of diffusion. Induced strained silicon technology should be considered when managing and enhancing mobility gain in devices with narrow channel widths. Thus, we fabricated a 20 nm silicon-based n-type metal-oxide-semiconductor field-effect transistor with a Si0.75Ge0.25 alloy channel and a + 3.0 GPa tensile contact etch stop layer as stressors. The transistor was utilized at different dummy gate arrays and dummy poly pitches. The fabricated device was subjected to oriented stress simulation, and the relationship between the piezoresistance effect and the stress component within the device channel was investigated. The best performance, which was 40% higher than that of conventional transistors, was observed in the transistor with 100 nm gate width.

KW - CESL

KW - Dummy gate array

KW - Finite element analysis

KW - SiGe channel

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