Diode string with reduced clamping voltage for efficient on-chip ESD protection

Chun Yu Lin, Wei Hao Fu

研究成果: 雜誌貢獻文章同行評審

1 引文 斯高帕斯(Scopus)

摘要

The standard steps of P- implantation and silicide block in the complementary metal-oxide semiconductor (CMOS) process are used in this design to implement the proposed diode string. The novel diode string realized by the diodes of P+ with N-well (P+/NW) and P- with N+ (P-/N+) is proposed in this letter. Besides, two diodes are merged together to form a silicon-controlled rectifier path to reduce the clamping voltage during electrostatic discharge (ESD) stress. The test devices of prior and proposed diode strings have been compared in a 0.18 μm CMOS process. With the higher current-handling ability and lower clamping voltage, the proposed diode string can be used as the efficient on-chip ESD protection device.

原文英語
文章編號7588053
頁(從 - 到)688-690
頁數3
期刊IEEE Transactions on Device and Materials Reliability
16
發行號4
DOIs
出版狀態已發佈 - 2016 十二月

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

指紋 深入研究「Diode string with reduced clamping voltage for efficient on-chip ESD protection」主題。共同形成了獨特的指紋。

引用此