Design of compact ESD protection circuit for V-band RF applications in a 65-nm CMOS technology

Chun Yu Lin, Li Wei Chu, Shiang Yu Tsai, Ming Dou Ker

研究成果: 雜誌貢獻文章

5 引文 斯高帕斯(Scopus)

摘要

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degraded the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, an on-chip ESD protection design must be included in the RF circuits. As the RF circuits operate in the higher frequency band, the parasitic effect from ESD protection circuit must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier with less RF performance degradation, two new ESD protection circuits were studied in a 65-nm CMOS process. Such compact ESD protection circuits have been successfully verified in silicon chip to achieve the 2-kV human-body-model ESD robustness with the low insertion loss in small layout area. With the better performances, the proposed ESD protection circuits were very suitable for V-band RF ESD protection.

原文英語
文章編號6155079
頁(從 - 到)554-561
頁數8
期刊IEEE Transactions on Device and Materials Reliability
12
發行號3
DOIs
出版狀態已發佈 - 2012 九月 14

    指紋

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Safety, Risk, Reliability and Quality
  • Electrical and Electronic Engineering

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