Design of a 5.3-GHz 31.3-dBm Fully Integrated CMOS Power Amplifier Using Folded Splitting and Combining Architecture

研究成果: 雜誌貢獻文章


A transformer (TF)-based folded radial power splitting and binary power combining architecture is developed for fully integrated CMOS PA design in this paper. The proposed folded splitting and combining architecture has advantages of in-phase RF signal splitting/combining scheme, compact size, uniform dc distribution, and symmetric dc current supply/return path. A 5.3-GHz fully integrated PA using the developed splitting/combining architecture is fabricated on a standard 0.18- \mu \text{m} CMOS technology. The CMOS PA transmits saturation power ( P-{\mathrm {sat}} ) of 31.3 dBm, output 1-dB compression point (OP1 dB) of 26.1 dBm, and power added efficiency (PAE) of 22% at 5.3 GHz. The measured small signal gain is 18.3 dB at 5.3 GHz. The EVM has been measured with IEEE 802.11ac WLAN modulated signals. Using the 20-MHz bandwidth OFDM 64-QAM modulated signal, the PA meets the WLAN EVM specification of 5.6% up to 20.4-dBm linear output power. To our knowledge, the CMOS PA achieves the highest P-{\mathrm {sat}} and OP1 dB with decent PAE among other reported fully integrated CMOS PAs around 5 GHz to date.

頁(從 - 到)1527-1536
期刊IEEE Transactions on Very Large Scale Integration (VLSI) Systems
出版狀態已發佈 - 2019 七月


ASJC Scopus subject areas

  • Software
  • Hardware and Architecture
  • Electrical and Electronic Engineering