Design and verification for dual issue digital signal processor

Cheng-Hung Lin, Chun Yu Lin, Shih Chieh Chang

    研究成果: 書貢獻/報告類型會議貢獻

    摘要

    Digital Signal Processor (DSP) has been widely used in processing video and audio streaming data. Due to the huge amount of streaming data, increasing throughput is the key issue in designing DSP architecture. One way to increase the throughput of a DSP is to increase the instruction level parallelism. To increase the instruction level parallelism, many architectures have been proposed and can be classified into two main approaches, the superscaler and the VLIW architectures. Among the hardware architectures, the VLIW attracts a lot of attention due to its simple hardware complexity. However, the VLIW architecture suffers from the explosion of instruction memories due to the overhead of instruction grouping. In this paper, we propose a novel DSP architecture which contains three pipelines and performs dynamic instruction grouping by hardware. The experimental results show that our architecture can reduce 13% of memory requiremnt on average while maintaining the same performance.

    原文英語
    主出版物標題2009 International SoC Design Conference, ISOCC 2009
    頁面536-539
    頁數4
    DOIs
    出版狀態已發佈 - 2009 十二月 1
    事件2009 International SoC Design Conference, ISOCC 2009 - Busan, 大韓民國
    持續時間: 2009 十一月 222009 十一月 24

    出版系列

    名字2009 International SoC Design Conference, ISOCC 2009

    其他

    其他2009 International SoC Design Conference, ISOCC 2009
    國家大韓民國
    城市Busan
    期間09/11/2209/11/24

    ASJC Scopus subject areas

    • Electrical and Electronic Engineering

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