@inproceedings{e722c18b22d34d2098a7776e2a119981,
title = "Dependence of N-Well Guard Ring Bias on Latch-up Failure Level in a HV/LV Mixed-Voltage CMOS IC",
abstract = "The additional N-well guard ring was often specified in the foundry's design rules to improve latch-up immunity of CMOS ICs. The impact of biasing the additional N-well guard ring on the latch-up immunity of a HV/LV mixed-voltage CMOS IC in a Bipolar-CMOS-DMOS (BCD) technology is investigated in this work. While intended to enhance latch-up immunity, an unexpected electrical overstress (EOS) failure is observed when the additional N-well guard ring is biased at low voltage during latch-up testing. Parasitic bipolar transistors between the high-voltage I/O devices and the additional N-well guard ring were activated to cause such an EOS failure. The effect of biasing the additional N-well guard rings on latch-up immunity is studied in detail through failure analysis.",
keywords = "Electrical overstress (EOS), additional guard ring, latch-up test, mixed-voltage IC",
author = "Ker, \{Chieh Chen\} and Hsu, \{Chen Wei\} and Lin, \{Chun Yu\} and Ker, \{Ming Dou\} and Wang, \{Chun Chi\} and Chiang, \{Tsung Yin\}",
note = "Publisher Copyright: {\textcopyright} 2025 IEEE.; 2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 ; Conference date: 21-04-2025 Through 24-04-2025",
year = "2025",
doi = "10.1109/VLSITSA64674.2025.11047198",
language = "English",
series = "2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
booktitle = "2025 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2025 - Proceedings of Technical Papers",
}