Compact FPGA implementation of 32-bits AES algorithm using block RAM

Chi Wu Huang*, Chi Jeng Chang, Mao Yuan Lin, Hung Yun Tai


研究成果: 書貢獻/報告類型會議論文篇章

24 引文 斯高帕斯(Scopus)


Hardware implementation of Advanced Encryption Standard (AES) algorithm has been in intensive discussion since its first publication by National Institute of Standards and Technology (NIST) in 2000, especially in high throughput over 1 Giga bits per second (Gbps). However, the studies of low area, low power and low cost implementations, which usually have throughput less than 1Gbps and use the datapath less than 32-bit, have been appearing recently in ASIC as well as in FPGA for wireless communication and embedded hardware application. This paper proposes a 32-bit datapath implementation in small Xilinx FPGA Chip (Spartan-3 XC3S200). It uses 148 slice, 11 Block RAMs (BRAMs) and achieves the data stream of 647 Mega bits per second ( Mbps) at 287 MHz working frequency. It obtains 3.4 times improvement to the best known similar design in terms of ratio throughput per area (Throughput/Area), and 20% smaller in slice area.

主出版物標題TENCON 2007 - 2007 IEEE Region 10 Conference
出版狀態已發佈 - 2007
事件IEEE Region 10 Conference, TENCON 2007 - Taipei, 臺灣
持續時間: 2007 10月 302007 11月 2


名字IEEE Region 10 Annual International Conference, Proceedings/TENCON


其他IEEE Region 10 Conference, TENCON 2007

ASJC Scopus subject areas

  • 電腦科學應用
  • 電氣與電子工程


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