Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology

Li Wei Chu, Chun Yu Lin, Shiang Yu Tsai, Ming Dou Ker, Ming Hsiang Song, Chewn Pu Jou, Tse Hua Lu, Jen Chou Tseng, Ming Hsien Tsai, Tsun Lai Hsu, Ping Fang Hung, Tzu Heng Chang

研究成果: 會議貢獻類型

1 引文 斯高帕斯(Scopus)

摘要

Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.

原文英語
頁面2127-2130
頁數4
DOIs
出版狀態已發佈 - 2012 九月 28
事件2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012 - Seoul, 大韓民國
持續時間: 2012 五月 202012 五月 23

其他

其他2012 IEEE International Symposium on Circuits and Systems, ISCAS 2012
國家大韓民國
城市Seoul
期間12/5/2012/5/23

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

指紋 深入研究「Compact and low-loss ESD protection design for V-band RF applications in a 65-nm CMOS technology」主題。共同形成了獨特的指紋。

引用此