COD: Alternative architectures for high speed packet switching

Current architectures for packet switches are approaching the limit of electronic switching speed. This raises the question of how best to utilize recent advances in photonic technology in order to enable higher speed operation. In this paper, we introduce cascaded optical delay line (COD) architectures for ultra high speed packet switching. The COD architectures utilize an extremely simple distributed electronic control algorithm to configure the states of 2 × 2 photonic switches and use optical fiber delay lines to temporarily buffer packets if necessary. The simplicity of the architectures may also make them suitable for "lightweight" all-electronic implementations. For optical implementations, the number of 2 × 2 photonic switches used is a significant factor determining cost. We present a "baseline" architecture for a 2 × 2 buffered packet switch that is work conserving (i.e. nonidling) and has the first-in, first-out (FIFO) property. If the arrival processes are independent and without memory, the maximum utilization factor is ρ, and the maximum acceptable packet loss probability is ε, then the required number of 2 × 2 photonic switches is O(log(ε)/log(γ)), where γ = ρ² /(ρ² + 4 - 4ρ). If we modify the baseline architecture by changing the delay line lengths then the system is no longer work conserving and loses the FIFO property, but the required number of 2 × 2 photonic switches is reduced to O(log [log (ε)/ log (γ)]). The required number of 2 × 2 photonic switches is essentially insensitive to the distribution of packet arrivals, but long delay lines are required for bursty traffic.