CDM ESD protection design with initial-on concept in nanoscale CMOS process

Chun Yu Lin*, Ming Dou Ker

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

8 引文 斯高帕斯(Scopus)

摘要

Integrated circuits (ICs) have been fabricated with thinner gate oxides to achieve higher speed and lower power consumption in nanoscale CMOS processes. However, the charged-device-model (CDM) electrostatic discharge (ESD) events became more critical because of the thinner gate oxide in nanoscale CMOS transistors and the larger die size for the system-on-chip (SoC) applications. Thus, effective on-chip ESD protection design against CDM ESD stresses has become more challenging to be implemented. A novel on-chip ESD protection design against CDM ESD events was proposed in this work, and its performance has been verified by the silicon chip fabricated in 55-nm CMOS process.

原文英語
主出版物標題IPFA 2010 - 17th International Symposium on the Physical and Failure Analysis of Integrated Circuits
DOIs
出版狀態已發佈 - 2010
對外發佈
事件17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010 - Singapore, 新加坡
持續時間: 2010 7月 52010 7月 9

出版系列

名字Proceedings of the International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA

其他

其他17th International Symposium on the Physical and Failure Analysis of Integrated Circuits, IPFA 2010
國家/地區新加坡
城市Singapore
期間2010/07/052010/07/09

ASJC Scopus subject areas

  • 電氣與電子工程

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