Capacitance matching by optimizing the geometry of a ferroelectric HfO₂-based gate for voltage amplification

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (W) and height/depth (H) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (ΔV_T = V_T, for –V_T,rev ~ 0) and achieve voltage amplification (A_V). The optimized conditions are found to be H = 19.3 nm and 24.3 nm to achieve the criterion with A_V > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (F_S). Tuning F_S can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum F_S value of 30 nm helps the FinFETs achieve capacitance matching with A_V > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for H_FinFET/W_FinFET ~ 3 and F_s/H_FinFET ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.