Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification

K. T. Chen, K. Y. Hsiang, C. Y. Liao, S. H. Chang, F. C. Hsieh, J. H. Liu, S. H. Chiang, H. Liang, S. T. Chang, M. H. Lee*

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

摘要

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (W) and height/depth (H) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (ΔVT = VT, for –VT,rev ~ 0) and achieve voltage amplification (AV). The optimized conditions are found to be H = 19.3 nm and 24.3 nm to achieve the criterion with AV > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (FS). Tuning FS can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum FS value of 30 nm helps the FinFETs achieve capacitance matching with AV > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for HFinFET/WFinFET ~ 3 and Fs/HFinFET ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.

原文英語
頁(從 - 到)1209-1215
頁數7
期刊Journal of Computational Electronics
20
發行號3
DOIs
出版狀態已發佈 - 2021 六月

ASJC Scopus subject areas

  • 電子、光磁材料
  • 原子與分子物理與光學
  • 建模與模擬
  • 電氣與電子工程

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