摘要
A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.
原文 | 英語 |
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文章編號 | 6531108 |
頁(從 - 到) | 291-295 |
頁數 | 5 |
期刊 | IEEE Transactions on Consumer Electronics |
卷 | 59 |
發行號 | 2 |
DOIs | |
出版狀態 | 已發佈 - 2013 |
ASJC Scopus subject areas
- 媒體技術
- 電氣與電子工程