C-slow retimed parallel histogram architectures for consumer imaging devices

Jose Cadenas, R. Sherratt, Pablo Huerta, Wen Chung Kao, Graham Megson

研究成果: 雜誌貢獻文章

5 引文 斯高帕斯(Scopus)

摘要

A parallel pipelined array of cells suitable for real-time computation of histograms is proposed. The cell architecture builds on previous work obtained via C-slow retiming techniques and can be clocked at 65 percent faster frequency than previous arrays. The new arrays can be exploited for higher throughput particularly when dual data rate sampling techniques are used to operate on single streams of data from image sensors. In this way, the new cell operates on a p-bit data bus which is more convenient for interfacing to camera sensors or to microprocessors in consumer digital cameras.

原文英語
文章編號6531108
頁(從 - 到)291-295
頁數5
期刊IEEE Transactions on Consumer Electronics
59
發行號2
DOIs
出版狀態已發佈 - 2013 七月 15

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

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