Block RAM based design of 8-bit AES operation modes

Chi Wu Huang, Hong You Chen*, Hsing Chang Yeh, Chi Jeng Chang


研究成果: 雜誌貢獻會議論文同行評審

2 引文 斯高帕斯(Scopus)


8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP).[1] It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.

頁(從 - 到)2848-2852
期刊Procedia Engineering
出版狀態已發佈 - 2012
事件2012 International Workshop on Information and Electronics Engineering, IWIEE 2012 - Harbin, 中国
持續時間: 2012 3月 102012 3月 11

ASJC Scopus subject areas

  • 建築與營造
  • 一般工程


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