8-bit AES implementation was first proposed in 2006 as Application Specific Instruction Processer (ASIP). It featured in low area design, for the increasing popular applications in wireless and embedded devices, based on the stored-program concept which the software programs run in an FPGA processor. This paper presents a direct FPGA implementation, in which the circuit areas varied depend on the algorithms and the implementing methods used. Our specific 8-bit implementation using three Block RAMs (BRAMs) achieves 88 slices in CFB/OFB mode and 134 slices in ECB mode which are better than or very close to 122 slices achieved by ASIP. The throughputs over 31 Mega bit per second (Mbps) are at least 14 times higher than 2.18 Mbps achieved by ASIP.
|頁（從 - 到）||2848-2852|
|出版狀態||已發佈 - 2012 三月 22|
|事件||2012 International Workshop on Information and Electronics Engineering, IWIEE 2012 - Harbin, 中国|
持續時間: 2012 三月 10 → 2012 三月 11
ASJC Scopus subject areas