Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and lowleakage diode string is proposed in this paper. The standard steps of P- implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P-/N+ diodes. The test devices of the proposed design have successfully been verified in the silicon chip. With the high ESD robustness, low leakage current, and small layout area, the proposed diode string can be a better solution for on-chip ESD protection applications.
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