Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices

Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.