Analysis of hot-carrier degradation in 0.25-μm surface-channel pMOSFET devices

Chuan H. Liu*, M. G. Chen, Shiang Huang-Lu, Y. J. Chang, K. Y. Fu

*此作品的通信作者

研究成果: 雜誌貢獻會議論文同行評審

4 引文 斯高帕斯(Scopus)

摘要

Three conventional hot-carrier (HC) stress conditions (i.e. stress at Vgs ≈ Vth, Vgs ≈ Vds/2, and Vgs = Vds) have been studied for a quarter-micrometer level surface-channel pMOSFET devices. It is shown that stress at Vgs ≈ Vth results in the worst-case damage, in which a 'turn-around' behavior for device parameters (such as Idsat, Vth, and gm) has been observed (this is not seen in 0.35-μm or longer p-channel devices to the best of our knowledge). This turn-around behavior could be explained by a two-step degradation model (i.e. electron trapping and charge compensation between electron trapping and interface-state generation). Moreover, similar to long-channel pMOSFET devices though the dominant degradation mechanism is somewhat different, DC device lifetime for 0.25-μm pMOSFET devices should be evaluated using gate current as a predictor rather than substrate current that has been suggested by some researchers.

原文英語
頁(從 - 到)82-85
頁數4
期刊International Symposium on VLSI Technology, Systems, and Applications, Proceedings
出版狀態已發佈 - 1999
事件Proceedings of the 1999 International Symposium on VLSI Technology, Systems, and Applications - Taipei, Taiwan
持續時間: 1999 六月 71999 六月 10

ASJC Scopus subject areas

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程

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