An X-band 9.75/10.6 GHz low-power phase-locked loop using 0.18-μm CMOS technology

Jeng Han Tsai, Chin Yi Hsu, Chia Hsiang Chao

研究成果: 書貢獻/報告類型會議論文篇章

4 引文 斯高帕斯(Scopus)

摘要

An X-band 9.75/10.6 GHz fully-integrated low-power consumption phase-locked loop (PLL) is designed and fabricated on standard 0.18-μm CMOS process. Through the band control circuit of the voltage control oscillator (VCO) and mode control of the 7-bit divide-by-128∼255 multi-modulus frequency divider (MMD), the PLL output frequency of 9.75 GHz and 10.6 GHz is synthesized successfully with a reference source of 12.5 MHz. Utilizing the transformer feedback VCO and high speed true single phase clock (TSPC) based 2/3 cell divider, the PLL achieves low power consumption of 24 mW with good phase noise. The measured closed loop phase noise of the PLL at a frequency offset of 10 MHz is-116.24 dBc/Hz and-122.64 dBc/Hz with center of 9.75 GHz and 10.6 GHz, respectively.

原文英語
主出版物標題European Microwave Week 2015
主出版物子標題"Freedom Through Microwaves", EuMW 2015 - Conference Proceedings; 2015 10th European Microwave Integrated Circuits Conference Proceedings, EuMIC
發行者Institute of Electrical and Electronics Engineers Inc.
頁面238-241
頁數4
ISBN(電子)9782874870408
DOIs
出版狀態已發佈 - 2015 十二月 2
事件10th European Microwave Integrated Circuits Conference, EuMIC 2015 - Paris, 法国
持續時間: 2015 九月 72015 九月 8

出版系列

名字European Microwave Week 2015:

其他

其他10th European Microwave Integrated Circuits Conference, EuMIC 2015
國家/地區法国
城市Paris
期間2015/09/072015/09/08

ASJC Scopus subject areas

  • 電腦網路與通信
  • 電氣與電子工程
  • 輻射

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