An ultra low-power 24 GHz Phase-lock-loop with low phase-noise VCO embedded in 0.18 μm CMOS process

Yu Hsuan Lin*, Jeng Han Tsai, Yen Hung Kuo, Tian Wei Huang

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

6 引文 斯高帕斯(Scopus)

摘要

A 24 GHz 29.8 mW Phase-lock-loop using 0.18 m CMOS technology is presented in this paper. To achieve the low-power issue and low phase-noise performance, a transformer feedback voltage control oscillator and a cascoded divider of injection-locked frequency divider and current mode logic divider for low voltage and low power are implemented. The phase-lock-loop phase noise was measured by 122 dBc/Hz at 10 MHz offset with low supply voltage and equipped the locking range of 20.80-23.37 GHz. The PLL dissipate 29.8 mW (only 13.3 mW in VCO + ILFD) and occupies the total area of 0.39 mm 2 without off-chip loop filter.

原文英語
主出版物標題Asia-Pacific Microwave Conference Proceedings, APMC 2011
頁面1630-1633
頁數4
出版狀態已發佈 - 2011
事件Asia-Pacific Microwave Conference, APMC 2011 - Melbourne, VIC, 澳大利亚
持續時間: 2011 十二月 52011 十二月 8

出版系列

名字Asia-Pacific Microwave Conference Proceedings, APMC

其他

其他Asia-Pacific Microwave Conference, APMC 2011
國家/地區澳大利亚
城市Melbourne, VIC
期間2011/12/052011/12/08

ASJC Scopus subject areas

  • 電氣與電子工程

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