An integrated Ka-band VCO and divide-by-4 frequency divider with 30.2% tuning range in 90-nm CMOS

Hamed Alsuraisry, Jen Hao Cheng, Wei Tsung Li, Jeng Han Tsai, Tian Wei Huang

研究成果: 雜誌貢獻文章

1 引文 斯高帕斯(Scopus)

摘要

This article presents a wideband phase-locked loop (PLL) front-end, which consists of a dual-core voltage-controlled oscillator (VCO) and a divide-by-four (D4) frequency divider in 90-nm CMOS technology. The switched inductors and varactor banks are used to enhance the tuning range of VCO. The D4 frequency divider is a body-biased injection-locked frequency divider (ILFD) cascoded with source-injection current mode logic (SICML) for wider locking range and lower power consumption. This PLL front-end demonstrates a 30.2% frequency tuning range (FTR) from 23.6 to 32 GHz and a phase noise of −101.22 dBc/Hz at 5.86 GHz with 1 MHz offset frequency. The output power is higher than −15 dBm among the operating bandwidth. The dc power consumption is 40.8 mW at 1.2 V and 1.5 V supply voltages.

原文英語
頁(從 - 到)1306-1309
頁數4
期刊Microwave and Optical Technology Letters
59
發行號6
DOIs
出版狀態已發佈 - 2017 六月 1

ASJC Scopus subject areas

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

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