TY - JOUR
T1 - An Integrated Detection Circuit for Transmission Coefficients
AU - Lee, Ming Che
AU - Huang, Chi Yo
N1 - Publisher Copyright:
© 2013 IEEE.
PY - 2020
Y1 - 2020
N2 - As the applications of radio-frequency (RF) circuits continue to prosper, scattering parameters (S-parameters) play an essential role in the verification of a variety of chips. The traditional way to measure the S-parameters of RF integrated circuits (RFICs) is by using vector network analyzers (VNA). However, measuring RFICs with VNAs is very expensive and likely to reduce the profits of IC products. An implementation of the embedded circuit for S-parameter measurement can greatly reduce the costs of using expensive VNAs. Another reason to embed the circuit for S-parameter measurement is to increase the portion of a chip that can be measured. Besides, novel technologies, such as three-dimensional ICs, will require advanced methods for on-chip verifications of RF circuits since many RF nodes may be buried deep inside a chip stack. In view of these needs, this paper proposes a simple network that can realize on-chip S21 measurements. The greatest advantages of this circuit are the easy implementation and technology independence. To verify the feasibility of the circuit, we fabricated the test chips by using the 0.18-μm IBM 7RF process. The measurement results show the expected behavior and demonstrate the feasibility of the design concept.
AB - As the applications of radio-frequency (RF) circuits continue to prosper, scattering parameters (S-parameters) play an essential role in the verification of a variety of chips. The traditional way to measure the S-parameters of RF integrated circuits (RFICs) is by using vector network analyzers (VNA). However, measuring RFICs with VNAs is very expensive and likely to reduce the profits of IC products. An implementation of the embedded circuit for S-parameter measurement can greatly reduce the costs of using expensive VNAs. Another reason to embed the circuit for S-parameter measurement is to increase the portion of a chip that can be measured. Besides, novel technologies, such as three-dimensional ICs, will require advanced methods for on-chip verifications of RF circuits since many RF nodes may be buried deep inside a chip stack. In view of these needs, this paper proposes a simple network that can realize on-chip S21 measurements. The greatest advantages of this circuit are the easy implementation and technology independence. To verify the feasibility of the circuit, we fabricated the test chips by using the 0.18-μm IBM 7RF process. The measurement results show the expected behavior and demonstrate the feasibility of the design concept.
KW - Radio frequency (RF)
KW - S-parameters
KW - automatic test equipment (ATE)
KW - bandwidth
KW - calibration
KW - device under test (DUT)
KW - divider (DIV)
KW - embedded testing
KW - integrated circuit (IC)
KW - vector network analyzer (VNA)
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U2 - 10.1109/ACCESS.2019.2961943
DO - 10.1109/ACCESS.2019.2961943
M3 - Article
AN - SCOPUS:85077290102
SN - 2169-3536
VL - 8
SP - 237
EP - 252
JO - IEEE Access
JF - IEEE Access
M1 - 8941034
ER -