An FPGA implementation of chaotic and edge enhanced error diffusion

Chung Yen Su*, You Lin Sie

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

4 引文 斯高帕斯(Scopus)

摘要

Digital halftoning plays a central role in getting more observable grey-levels for either the innovative electronic paper or other less level devices. The hardware implementation of digital halftoning is, however, seldom fully explored. In this paper, we propose a novel implementation of digital halftoning by means of error diffusion. The proposed scheme not only can perform a new method called chaotic and edge enhanced error diffusion, but also can be reduced to perform the conventional Floyd-Steinberg error diffusion. Best of all, our new scheme can produce halftone images with lower worm-like artifacts and sharper image edges. This scheme is mainly composed of four components: gradientbased edge detection, chaotic threshold generation, edge enhanced quantization, and error diffusion. Each circuit design of the four components is illustrated for the first time. Besides, we demonstrate the hardware performance of our scheme by using a field programmable gate array (FPGA) chip to offer possibly further applications.

原文英語
文章編號5606322
頁(從 - 到)1755-1762
頁數8
期刊IEEE Transactions on Consumer Electronics
56
發行號3
DOIs
出版狀態已發佈 - 2010 八月

ASJC Scopus subject areas

  • 媒體技術
  • 電氣與電子工程

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