An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo; Han Chiang Lin

doi:10.1109/ISCE.2013.6570165

An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo, Han Chiang Lin

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

摘要

This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and V_cm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

原文	英語
主出版物標題	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
頁面	167-168
頁數	2
DOIs	https://doi.org/10.1109/ISCE.2013.6570165
出版狀態	已發佈 - 2013
事件	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, 臺灣持續時間: 2013 6月 3 → 2013 6月 6

出版系列

名字	Proceedings of the International Symposium on Consumer Electronics, ISCE

其他

其他	2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
國家/地區	臺灣
城市	Hsinchu
期間	2013/06/03 → 2013/06/06

ASJC Scopus subject areas

一般工程

UN SDG

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存取文件

10.1109/ISCE.2013.6570165

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Kuo, CH & Lin, HC 2013, An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching. 於 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013., 6570165, Proceedings of the International Symposium on Consumer Electronics, ISCE, 頁 167-168, 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013, Hsinchu, 臺灣, 2013/06/03. https://doi.org/10.1109/ISCE.2013.6570165

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abstract = "This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.",

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AB - This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

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BT - 2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013

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ER -

An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

摘要

出版系列

其他

ASJC Scopus subject areas

UN SDG

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