An energy-efficiency split SAR ADC with floating capacitor and unit-cap bias-switching

Chien Hung Kuo, Han Chiang Lin

研究成果: 書貢獻/報告類型會議論文篇章

摘要

This paper presents an energy-efficient and area-saving split successive approximation register analog-to-digital converter (SSAR ADC). By the use of the floating capacitor and Vcm sampling schemes, the DAC switched capacitors of the SSAR ADC can be reduced. With the use of the proposed unit-cap bias-switching, one more bit of output resolution can be improved. Comparing to the traditional SSAR ADC, the proposed SSAR can save 50.76% of chip area and efficiently reduce the consumption of switching energy.

原文英語
主出版物標題2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
頁面167-168
頁數2
DOIs
出版狀態已發佈 - 2013 九月 11
事件2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013 - Hsinchu, 臺灣
持續時間: 2013 六月 32013 六月 6

出版系列

名字Proceedings of the International Symposium on Consumer Electronics, ISCE

其他

其他2013 IEEE 17th International Symposium on Consumer Electronics, ISCE 2013
國家/地區臺灣
城市Hsinchu
期間2013/06/032013/06/06

ASJC Scopus subject areas

  • 工程 (全部)

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