An efficient VLSI architecture for H.264 variable block size motion estimation

Chien Min Ou, Chian Feng Le, Wen Jyi Hwang

研究成果: 雜誌貢獻文章

69 引文 斯高帕斯(Scopus)

摘要

This paper proposes a novel flexible VLSI architecture for the implementation of variable block size motion estimation (VBSME). The architecture is able to perform a full motion search on integral multiples of 4×4 blocks sizes. To use the architecture, each 16×16 macroblock of the source frames should be partitioned into sixteen 4×4 non-overlapping subblocks, called primitive subblocks. The architecture contains sixteen modules and one VBSME processor. Each module, realized by cascading 1D systolic arrays, is responsible for the block-matching operations of a different primitive subblock. The realization has the advantages of high throughput, high flexibility and 100 % processing element (PE) utilization. The motion estimation of all the primitive subblocks are performed in parallel. Because these primitive subblocks can be used to form the 41 subblocks of different sizes specified by the H.264, the VBSME processor is employed to concurrently compute the sums of absolute differences (SADs) of all the 41 subblocks from the SADs of the primitive subblocks. This new architecture has lower latency and higher throughput over other exiting VBSME architectures for the hardware implementation of H.264 encoders.

原文英語
頁(從 - 到)1291-1299
頁數9
期刊IEEE Transactions on Consumer Electronics
51
發行號4
DOIs
出版狀態已發佈 - 2005 十一月 1

    指紋

ASJC Scopus subject areas

  • Media Technology
  • Electrical and Electronic Engineering

引用此