An efficient pipelined architecture for fast competitive learning

Hui Ya Li, Chia Lung Hung, Wen Jyi Hwang

研究成果: 書貢獻/報告類型會議貢獻

1 引文 斯高帕斯(Scopus)

摘要

This paper presents a novel pipelined architecture for fast competitive learning (CL). It is used as a hardware accelerator in a system on programmable chip (SOPC) for reducing the computational time. In the architecture, a novel codeword swapping scheme is adopted so that both neuron competition processes for different training vectors can be operated concurrently. The neuron updating process is based on a hardware divider with simple table lookup operations. The divider performs finite precision calculation for area cost reduction at the expense of slight degradation in training performance. Experimental results show that the CPU time is lower than that of other hardware or software implementations running the CL training program with or without the support of custom hardware.

原文英語
主出版物標題Algorithms and Architectures for Parallel Processing - 10th International Conference, ICA3PP 2010, Workshops
頁面381-390
頁數10
版本PART 2
DOIs
出版狀態已發佈 - 2010 十二月 1
事件10th International Conference Algorithms and Architectures for Parallel Processing, ICA3PP 2010 - Busan, 大韓民國
持續時間: 2010 五月 212010 五月 23

出版系列

名字Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
號碼PART 2
6082 LNCS
ISSN(列印)0302-9743
ISSN(電子)1611-3349

其他

其他10th International Conference Algorithms and Architectures for Parallel Processing, ICA3PP 2010
國家大韓民國
城市Busan
期間10/5/2110/5/23

ASJC Scopus subject areas

  • Theoretical Computer Science
  • Computer Science(all)

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