An efficient hardware circuit for spike sorting based on competitive learning networks

Huan Yuan Chen, Chih Chang Chen, Wen Jyi Hwang*


研究成果: 雜誌貢獻期刊論文同行評審

2 引文 斯高帕斯(Scopus)


This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

期刊Sensors (Switzerland)
出版狀態已發佈 - 2017 十月

ASJC Scopus subject areas

  • 分析化學
  • 生物化學
  • 原子與分子物理與光學
  • 儀器
  • 電氣與電子工程


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