TY - GEN
T1 - An efficient FPGA-based architecture for convolutional neural networks
AU - Hwang, Wen Jyi
AU - Jhang, Yun Jie
AU - Tai, Tsung Ming
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/10/19
Y1 - 2017/10/19
N2 - The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.
AB - The goal of this paper is to implement an efficient FPGA-based hardware architectures for the design of fast artificial vision systems. The proposed architecture is capable of performing classification operations of a Convolutional Neural Network (CNN) in realtime. To show the effectiveness of the architecture, some design examples such as hand posture recognition, character recognition, and face recognition are provided. Experimental results show that the proposed architecture is well suited for embedded artificial computer vision systems requiring high portability, high computational speed, and accurate classification.
KW - Artificial vision systems
KW - Convolutional neural networks
KW - Field programmable gate array
KW - Hardware architecture
KW - Pipeline operations
UR - http://www.scopus.com/inward/record.url?scp=85043276060&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85043276060&partnerID=8YFLogxK
U2 - 10.1109/TSP.2017.8076054
DO - 10.1109/TSP.2017.8076054
M3 - Conference contribution
AN - SCOPUS:85043276060
T3 - 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
SP - 582
EP - 588
BT - 2017 40th International Conference on Telecommunications and Signal Processing, TSP 2017
A2 - Herencsar, Norbert
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 40th International Conference on Telecommunications and Signal Processing, TSP 2017
Y2 - 5 July 2017 through 7 July 2017
ER -