Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

C. H. Cheng; K. I. Chou; Albert Chin

doi:10.1016/j.sse.2013.02.003

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO ₂ gate stack

C. H. Cheng^*
, K. I. Chou
, Albert Chin

^*此作品的通信作者

機電工程學系

研究成果: 雜誌貢獻 › 期刊論文 › 同行評審

4 引文斯高帕斯（Scopus）

摘要

We report a gate-first TiLaO/CeO₂ n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V_t) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO ₂ interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO₂ with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

原文	英語
頁（從 - 到）	111-114
頁數	4
期刊	Solid-State Electronics
卷	82
DOIs	https://doi.org/10.1016/j.sse.2013.02.003
出版狀態	已發佈 - 2013

ASJC Scopus subject areas

電子、光磁材料
凝聚態物理學
電氣與電子工程
材料化學

存取文件

10.1016/j.sse.2013.02.003

其它文件與鏈接

引用此

@article{8d5f02ae0a744c78b85d08576b79ab90,

title = "Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack",

abstract = "We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.",

keywords = "CeO, Gate first, Small EOT, TiLaO",

author = "Cheng, \{C. H.\} and Chou, \{K. I.\} and Albert Chin",

year = "2013",

doi = "10.1016/j.sse.2013.02.003",

language = "English",

volume = "82",

pages = "111--114",

journal = "Solid-State Electronics",

issn = "0038-1101",

publisher = "Elsevier Limited",

}

TY - JOUR

T1 - Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

AU - Cheng, C. H.

AU - Chou, K. I.

AU - Chin, Albert

PY - 2013

Y1 - 2013

N2 - We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

AB - We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

KW - CeO

KW - Gate first

KW - Small EOT

KW - TiLaO

UR - https://www.scopus.com/pages/publications/84875136427

UR - https://www.scopus.com/pages/publications/84875136427#tab=citedBy

U2 - 10.1016/j.sse.2013.02.003

DO - 10.1016/j.sse.2013.02.003

M3 - Article

AN - SCOPUS:84875136427

SN - 0038-1101

VL - 82

SP - 111

EP - 114

JO - Solid-State Electronics

JF - Solid-State Electronics

ER -

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

摘要

ASJC Scopus subject areas

存取文件

其它文件與鏈接

指紋

引用此

Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO ₂ gate stack