Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO 2 gate stack

Chun-Hu Cheng*, K. I. Chou, Albert Chin

*此作品的通信作者

研究成果: 雜誌貢獻期刊論文同行評審

3 引文 斯高帕斯(Scopus)

摘要

We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO 2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

原文英語
頁(從 - 到)111-114
頁數4
期刊Solid-State Electronics
82
DOIs
出版狀態已發佈 - 2013 三月 25

ASJC Scopus subject areas

  • 電子、光磁材料
  • 凝聚態物理學
  • 電氣與電子工程
  • 材料化學

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