A X-band frequency synthesizer with 2-bit control mode is implemented in standard 0.18-μm 1P6M CMOS process. A cascoded topology of voltage control oscillator (VCO) and first stage current mode logic (CML) divider is adopted for current reuse, low power, and robust tracking between VCO and the frequency divider. The measured in-band phase noise of the synthesizer is -75.06 dBc/Hz at a frequency offset of 100 kHz and out-of-band phase noise is -119.8 dBc/Hz at a frequency offset of 10 MHz. The total power consumption is 36.75 mW. The chip size is 0.745 × 0.76mm2.