A simulation study on dispatching rules in semiconductor wafer fabrication facilities with due date-based objectives

Tsung Che Chiang*, Li Chen Fu

*此作品的通信作者

研究成果: 書貢獻/報告類型會議論文篇章

5 引文 斯高帕斯(Scopus)

摘要

This paper addresses the lot scheduling problem in the semiconductor wafer fabrication facilities. We provide a simulation study to examine the performance of sixteen existing dispatching rules on the tardy rate, mean tardiness, and the maximum tardiness. A public and representative test bed, the MIMAC (Measurement and Improvement of MAnufacturing Capacities) test bed is used. The best rules with respect to each objective are identified through the experiments, and some Undings are provided to be guidelines for designing new dispatching rules.

原文英語
主出版物標題2006 IEEE International Conference on Systems, Man and Cybernetics
發行者Institute of Electrical and Electronics Engineers Inc.
頁面4660-4665
頁數6
ISBN(列印)1424401003, 9781424401000
DOIs
出版狀態已發佈 - 2006 一月 1
事件2006 IEEE International Conference on Systems, Man and Cybernetics - Taipei, 臺灣
持續時間: 2006 十月 82006 十月 11

出版系列

名字Conference Proceedings - IEEE International Conference on Systems, Man and Cybernetics
6
ISSN(列印)1062-922X

其他

其他2006 IEEE International Conference on Systems, Man and Cybernetics
國家/地區臺灣
城市Taipei
期間2006/10/082006/10/11

ASJC Scopus subject areas

  • 工程 (全部)

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