A quadruple-sampling second-order delta-sigma modulator

Chien Hung Kuo, Wei Wei Tseng

研究成果: 書貢獻/報告類型會議論文篇章

摘要

In this paper, a 1.8-V 3-bit quadruple-sampling delta-sigma modulator for audio application is presented. To performance high-resolution and low-cost modulator, a single opamp is used to complete the integration with four phases. Since the phase difference between any two succeeding clocks is 90 degrees, the sampling rate will be four times of clock frequency. The effective integration time can also be increased, and thus relaxing the requirements of opamp. From the simulation results, the proposed modulator achieves a peak SNDR of 104.5 dB for 20-kHz signal bandwidth under 1.8-V supply voltage and 2.56 MHz clock rate.

原文英語
主出版物標題2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509023332
DOIs
出版狀態已發佈 - 2016 十二月 27
事件5th IEEE Global Conference on Consumer Electronics, GCCE 2016 - Kyoto, 日本
持續時間: 2016 十月 112016 十月 14

出版系列

名字2016 IEEE 5th Global Conference on Consumer Electronics, GCCE 2016

其他

其他5th IEEE Global Conference on Consumer Electronics, GCCE 2016
國家/地區日本
城市Kyoto
期間2016/10/112016/10/14

ASJC Scopus subject areas

  • 訊號處理
  • 電氣與電子工程
  • 電腦科學應用
  • 硬體和架構
  • 儀器

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