The trilateral noise filter is capable of reducing both Gaussian and impulse image noise. The filter combines domain filter, range filter, and rank-ordered absolute differences (ROAD) measurement into an integrated weighting function. The main issue of applying such a powerful noise filter on real-time imaging systems is that its time complexity is extremely high. A possible way to remedying the problem is designing a dedicated hardware accelerator. In this paper, we propose a new pipelined architecture design for trilateral noise filtering. By using a bitwise operation for ROAD calculation and piecewise linear approximation for exponential function evaluation, the performance of these two time consuming operations are improved dramatically. The proposed architecture has been verified on a Xilinx FPGA board, and the system clock of this design can achieve 96.5 MHz which can process 4 MPixels/second.
|頁（從 - 到）||3415-3418|
|期刊||Proceedings - IEEE International Symposium on Circuits and Systems|
|出版狀態||已發佈 - 2007 一月 1|
|事件||2007 IEEE International Symposium on Circuits and Systems, ISCAS 2007 - New Orleans, LA, 美国|
持續時間: 2007 五月 27 → 2007 五月 30
ASJC Scopus subject areas