A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh; Y. C. Fan; K. Y. Chang; C. H. Liu; C. H. Chien; Steve S. Chung

doi:10.1109/VLSI-TSA.2017.7942487

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Y. C. Fan, K. Y. Chang, C. H. Liu, C. H. Chien, Steve S. Chung

機電工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

1 引文斯高帕斯（Scopus）

摘要

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the I_on current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of I_on, comparable to those of LP planar CMOS devices, 0.1 nA/um of I_off, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

原文	英語
主出版物標題	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781509058051
DOIs	https://doi.org/10.1109/VLSI-TSA.2017.7942487
出版狀態	已發佈 - 2017 6月 7
事件	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, 臺灣持續時間: 2017 4月 24 → 2017 4月 27

出版系列

名字	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

其他

其他	2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
國家/地區	臺灣
城市	Hsinchu
期間	2017/04/24 → 2017/04/27

ASJC Scopus subject areas

硬體和架構
電氣與電子工程

存取文件

10.1109/VLSI-TSA.2017.7942487

其它文件與鏈接

引用此

Hsieh, E. R., Fan, Y. C., Chang, K. Y., Liu, C. H., Chien, C. H., & Chung, S. S. (2017). A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 於 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 文章 7942487 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2017.7942487

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. / Hsieh, E. R.; Fan, Y. C.; Chang, K. Y. 等.
2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. 7942487 (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Hsieh, ER, Fan, YC, Chang, KY, Liu, CH, Chien, CH & Chung, SS 2017, A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 於 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017., 7942487, 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Institute of Electrical and Electronics Engineers Inc., 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017, Hsinchu, 臺灣, 2017/04/24. https://doi.org/10.1109/VLSI-TSA.2017.7942487

Hsieh ER, Fan YC, Chang KY, Liu CH, Chien CH, Chung SS. A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 於 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc. 2017. 7942487. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). doi: 10.1109/VLSI-TSA.2017.7942487

Hsieh, E. R. ; Fan, Y. C. ; Chang, K. Y. 等. / A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017. Institute of Electrical and Electronics Engineers Inc., 2017. (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017).

@inproceedings{9719cdd469c74ed6a083c6307b8e3b84,

title = "A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications",

abstract = "A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.",

author = "Hsieh, {E. R.} and Fan, {Y. C.} and Chang, {K. Y.} and Liu, {C. H.} and Chien, {C. H.} and Chung, {Steve S.}",

note = "Publisher Copyright: {\textcopyright} 2017 IEEE.; 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 ; Conference date: 24-04-2017 Through 27-04-2017",

year = "2017",

month = jun,

day = "7",

doi = "10.1109/VLSI-TSA.2017.7942487",

language = "English",

series = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

booktitle = "2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017",

}

TY - GEN

T1 - A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

AU - Hsieh, E. R.

AU - Fan, Y. C.

AU - Chang, K. Y.

AU - Liu, C. H.

AU - Chien, C. H.

AU - Chung, Steve S.

PY - 2017/6/7

Y1 - 2017/6/7

N2 - A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

AB - A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

UR - http://www.scopus.com/inward/record.url?scp=85023185224&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85023185224&partnerID=8YFLogxK

U2 - 10.1109/VLSI-TSA.2017.7942487

DO - 10.1109/VLSI-TSA.2017.7942487

M3 - Conference contribution

AN - SCOPUS:85023185224

T3 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

BT - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

Y2 - 24 April 2017 through 27 April 2017

ER -

A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

摘要

出版系列

其他

ASJC Scopus subject areas

存取文件

其它文件與鏈接

指紋

引用此