A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications

E. R. Hsieh, Y. C. Fan, K. Y. Chang, C. H. Liu, C. H. Chien, Steve S. Chung

研究成果: 書貢獻/報告類型會議貢獻

摘要

A novel complementary tunneling FET (C-TFET) has been designed and targeted for the low power and appropriate performance applications (Apps). In this new architecture of C-TFET, the drain and source (D/S) are configured as a staggered structure to increase the tunneling current, and the conventional p-i-n junction C-TFET has been modified as a p-n junction to further enhance the Ion current. The results show that new design can achieve 310uA/um(n), 440uA/um(p) TFETs of Ion, comparable to those of LP planar CMOS devices, 0.1 nA/um of Ioff, while excellent S.S.(<10mV/dec) at Vdd= 0.7V, which will be a promising candidate for the low-power and appropriate performance apps in the next decade.

原文英語
主出版物標題2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509058051
DOIs
出版狀態已發佈 - 2017 六月 7
對外發佈Yes
事件2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 - Hsinchu, 臺灣
持續時間: 2017 四月 242017 四月 27

出版系列

名字2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017

其他

其他2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017
國家臺灣
城市Hsinchu
期間17/4/2417/4/27

ASJC Scopus subject areas

  • Hardware and Architecture
  • Electrical and Electronic Engineering

指紋 深入研究「A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications」主題。共同形成了獨特的指紋。

  • 引用此

    Hsieh, E. R., Fan, Y. C., Chang, K. Y., Liu, C. H., Chien, C. H., & Chung, S. S. (2017). A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications. 於 2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017 [7942487] (2017 International Symposium on VLSI Technology, Systems and Application, VLSI-TSA 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSI-TSA.2017.7942487