In this paper, a fast-locking delay-locked loop (DLL) with jitter-bounded feature is presented. In the proposed fast-locking mechanism, a frequency estimator and a programmable voltage circuit are developed to rapidly switch the control node of voltage-controlled delay line to a voltage level near the final required value. After that, the DLL output will be quickly locked by the following charge pumping on the loop filter. In the jitter-bounded approach, two phase-frequency detectors and a tunable delay are employed to hold the output clock jitter between two reference inputs after the DLL is locked. Furthermore, to enhance the flexibility of the presented DLL, a frequency multiplier with fewer active devices is also developed to provide high-frequency clock output for wideband applications. The presented DLL is implemented in a 0.18-m 1P6M CMOS technology. The active area without contact pads is 0.34 × 0.41 mm2. A minimum lock time of six clock cycles is measured from no reference input to locked state. The output frequency ranges of the DLL and the frequency multiplier can be measured from 200 to 400 MHz and from 1 to 2 GHz, respectively. The power dissipation of the presented DLL is 31.5 mW at a 1.8 V supply voltage.
|頁（從 - 到）||51-59|
|期刊||IEEE Transactions on Ultrasonics, Ferroelectrics, and Frequency Control|
|出版狀態||已發佈 - 2011 一月|
ASJC Scopus subject areas