TY - GEN
T1 - A multi-band delay-locked loop with fast-locked and jitter-bounded features
AU - Kuo, Chien Hung
AU - Lin, Meng Feng
AU - Chen, Chien Hung
PY - 2008
Y1 - 2008
N2 - In this paper, a multi-band delay-locked loop with fastlocked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLLbased frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 μm 1P6M CMOS process. The core area excluding PADs is 0.34× 0.41 mm 2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.
AB - In this paper, a multi-band delay-locked loop with fastlocked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLLbased frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 μm 1P6M CMOS process. The core area excluding PADs is 0.34× 0.41 mm 2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.
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U2 - 10.1109/ASSCC.2008.4708822
DO - 10.1109/ASSCC.2008.4708822
M3 - Conference contribution
AN - SCOPUS:67649908829
SN - 9781424426058
T3 - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
SP - 441
EP - 444
BT - Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
T2 - 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
Y2 - 3 November 2008 through 5 November 2008
ER -