A multi-band delay-locked loop with fast-locked and jitter-bounded features

Chien Hung Kuo, Meng Feng Lin, Chien Hung Chen

研究成果: 書貢獻/報告類型會議論文篇章

2 引文 斯高帕斯(Scopus)

摘要

In this paper, a multi-band delay-locked loop with fastlocked and jitter-bounded features is presented. A programmable charging voltage circuit to the loop filter is developed to accelerate the locking of DLL. The shortest lock time of the proposed DLL is six clock cycles from the unlocked state. In the presented DLL, two phase-frequency detectors with a tunable delay cell are used to reduce the output clock jitter. A new DLLbased frequency multiplier with less active devices is also proposed to promote the operating frequency range from 200 MHz to 2 GHz. The presented DLL is implemented in a 0.18 μm 1P6M CMOS process. The core area excluding PADs is 0.34× 0.41 mm 2. The power consumption of the presented DLL is 31.5 mW at a 1.8 V of supply voltage.

原文英語
主出版物標題Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
頁面441-444
頁數4
DOIs
出版狀態已發佈 - 2008 十二月 1
事件2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008 - Fukuoka, 日本
持續時間: 2008 十一月 32008 十一月 5

出版系列

名字Proceedings of 2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008

其他

其他2008 IEEE Asian Solid-State Circuits Conference, A-SSCC 2008
國家/地區日本
城市Fukuoka
期間2008/11/032008/11/05

ASJC Scopus subject areas

  • 硬體和架構
  • 電氣與電子工程

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