A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang; Chia Hui Yu; Jeng Han Tsai; Tian Wei Huang

doi:10.1109/APMC.2012.6421689

A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang^*, Chia Hui Yu, Jeng Han Tsai, Tian Wei Huang

^*此作品的通信作者

電機工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

4 引文斯高帕斯（Scopus）

摘要

A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

原文	英語
主出版物標題	2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
頁面	643-645
頁數	3
DOIs	https://doi.org/10.1109/APMC.2012.6421689
出版狀態	已發佈 - 2012
事件	2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, 臺灣持續時間: 2012 12月 4 → 2012 12月 7

出版系列

名字	Asia-Pacific Microwave Conference Proceedings, APMC

其他

其他	2012 Asia-Pacific Microwave Conference, APMC 2012
國家/地區	臺灣
城市	Kaohsiung
期間	2012/12/04 → 2012/12/07

ASJC Scopus subject areas

電氣與電子工程

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10.1109/APMC.2012.6421689

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引用此

Huang, M, Yu, CH, Tsai, JH & Huang, TW 2012, A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology. 於 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings., 6421689, Asia-Pacific Microwave Conference Proceedings, APMC, 頁 643-645, 2012 Asia-Pacific Microwave Conference, APMC 2012, Kaohsiung, 臺灣, 2012/12/04. https://doi.org/10.1109/APMC.2012.6421689

@inproceedings{139efc91443b4332a63df0277a4dc476,

title = "A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology",

abstract = "A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).",

keywords = "Phase-lock-loop, gain-boosted, injection-locked frequency divider, transformer-feedback, voltage control oscillator",

author = "Min Huang and Yu, {Chia Hui} and Tsai, {Jeng Han} and Huang, {Tian Wei}",

year = "2012",

doi = "10.1109/APMC.2012.6421689",

language = "English",

isbn = "9781457713309",

series = "Asia-Pacific Microwave Conference Proceedings, APMC",

pages = "643--645",

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note = "2012 Asia-Pacific Microwave Conference, APMC 2012 ; Conference date: 04-12-2012 Through 07-12-2012",

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TY - GEN

T1 - A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

AU - Huang, Min

AU - Yu, Chia Hui

AU - Tsai, Jeng Han

AU - Huang, Tian Wei

PY - 2012

Y1 - 2012

N2 - A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

AB - A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

KW - Phase-lock-loop

KW - gain-boosted

KW - injection-locked frequency divider

KW - transformer-feedback

KW - voltage control oscillator

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U2 - 10.1109/APMC.2012.6421689

DO - 10.1109/APMC.2012.6421689

M3 - Conference contribution

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SN - 9781457713309

T3 - Asia-Pacific Microwave Conference Proceedings, APMC

SP - 643

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BT - 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings

T2 - 2012 Asia-Pacific Microwave Conference, APMC 2012

Y2 - 4 December 2012 through 7 December 2012

ER -

A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

摘要

出版系列

其他

ASJC Scopus subject areas

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其它文件與鏈接

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