A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology

Min Huang, Chia Hui Yu, Jeng Han Tsai, Tian Wei Huang

研究成果: 書貢獻/報告類型會議貢獻

3 引文 斯高帕斯(Scopus)

摘要

A 24 GHz PLL using 0.18-μm CMOS technology is presented in this paper. To achieve the low-power consumption and low phase-noise performance, a transformerfeedback voltage control oscillator (TF-VCO) and a cascoded frequency divider including injection-locked frequency divider (ILFD) and current mode logic divider (CML) are implemented. Further- more, the gain-boosted technique was adopted in charge pump to reduce current mismatch. The phase noise of proposed PLL is measured by -83.79 dBc/Hz at 1 MHz offset and -123.61 dBc/Hz at 10 MHz offset. The power consumption is 29.8 mW (only 13.3 mW in VCO and ILFD).

原文英語
主出版物標題2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings
頁面643-645
頁數3
DOIs
出版狀態已發佈 - 2012 十二月 1
事件2012 Asia-Pacific Microwave Conference, APMC 2012 - Kaohsiung, 臺灣
持續時間: 2012 十二月 42012 十二月 7

出版系列

名字Asia-Pacific Microwave Conference Proceedings, APMC

其他

其他2012 Asia-Pacific Microwave Conference, APMC 2012
國家臺灣
城市Kaohsiung
期間12/12/412/12/7

    指紋

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

引用此

Huang, M., Yu, C. H., Tsai, J. H., & Huang, T. W. (2012). A low-power 24 GHz phase lock loop with gain-boosted charge pump embedded in 0.18 μm COMS technology. 於 2012 Asia-Pacific Microwave Conference, APMC 2012 - Proceedings (頁 643-645). [6421689] (Asia-Pacific Microwave Conference Proceedings, APMC). https://doi.org/10.1109/APMC.2012.6421689