A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

Ya Chi Cheng; Hung Bin Chen; Chun Yen Chang; Chun Hu Cheng; Yi Jia Shih; Yung Chun Wu

doi:10.1109/VLSIT.2016.7573429

A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

Ya Chi Cheng, Hung Bin Chen, Chun Yen Chang, Chun Hu Cheng, Yi Jia Shih, Yung Chun Wu

機電工程學系

研究成果: 書貢獻/報告類型 › 會議論文篇章

12 引文斯高帕斯（Scopus）

摘要

This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I_on/I_off current ratio (>10⁹), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (V_th) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

原文	英語
主出版物標題	2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
發行者	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子）	9781509006373
DOIs	https://doi.org/10.1109/VLSIT.2016.7573429
出版狀態	已發佈 - 2016 9月 21
事件	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, 美国持續時間: 2016 6月 13 → 2016 6月 16

出版系列

名字	Digest of Technical Papers - Symposium on VLSI Technology
卷	2016-September
ISSN（列印）	0743-1562

其他

其他	36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
國家/地區	美国
城市	Honolulu
期間	2016/06/13 → 2016/06/16

ASJC Scopus subject areas

電氣與電子工程

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10.1109/VLSIT.2016.7573429

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引用此

Cheng, Y. C., Chen, H. B., Chang, C. Y., Cheng, C. H., Shih, Y. J., & Wu, Y. C. (2016). A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. 於 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 文章 7573429 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2016.7573429

A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. / Cheng, Ya Chi; Chen, Hung Bin; Chang, Chun Yen 等.
2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016. 7573429 (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2016-September).

研究成果: 書貢獻/報告類型 › 會議論文篇章

Cheng, YC, Chen, HB, Chang, CY, Cheng, CH, Shih, YJ & Wu, YC 2016, A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. 於 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016., 7573429, Digest of Technical Papers - Symposium on VLSI Technology, 卷 2016-September, Institute of Electrical and Electronics Engineers Inc., 36th IEEE Symposium on VLSI Technology, VLSI Technology 2016, Honolulu, 美国, 2016/06/13. https://doi.org/10.1109/VLSIT.2016.7573429

Cheng YC, Chen HB, Chang CY, Cheng CH, Shih YJ, Wu YC. A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. 於 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc. 2016. 7573429. (Digest of Technical Papers - Symposium on VLSI Technology). doi: 10.1109/VLSIT.2016.7573429

Cheng, Ya Chi ; Chen, Hung Bin ; Chang, Chun Yen 等. / A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016. Institute of Electrical and Electronics Engineers Inc., 2016. (Digest of Technical Papers - Symposium on VLSI Technology).

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title = "A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs",

abstract = "This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.",

author = "Cheng, {Ya Chi} and Chen, {Hung Bin} and Chang, {Chun Yen} and Cheng, {Chun Hu} and Shih, {Yi Jia} and Wu, {Yung Chun}",

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AU - Cheng, Chun Hu

AU - Shih, Yi Jia

AU - Wu, Yung Chun

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N2 - This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

AB - This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

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A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

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