A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs

Ya Chi Cheng, Hung Bin Chen, Chun Yen Chang, Chun Hu Cheng, Yi Jia Shih, Yung Chun Wu

研究成果: 書貢獻/報告類型會議貢獻

9 引文 斯高帕斯(Scopus)

摘要

This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high Ion/Ioff current ratio (>109), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.

原文英語
主出版物標題2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016
發行者Institute of Electrical and Electronics Engineers Inc.
ISBN(電子)9781509006373
DOIs
出版狀態已發佈 - 2016 九月 21
事件36th IEEE Symposium on VLSI Technology, VLSI Technology 2016 - Honolulu, 美国
持續時間: 2016 六月 132016 六月 16

出版系列

名字Digest of Technical Papers - Symposium on VLSI Technology
2016-September
ISSN(列印)0743-1562

其他

其他36th IEEE Symposium on VLSI Technology, VLSI Technology 2016
國家美国
城市Honolulu
期間16/6/1316/6/16

ASJC Scopus subject areas

  • Electrical and Electronic Engineering

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    Cheng, Y. C., Chen, H. B., Chang, C. Y., Cheng, C. H., Shih, Y. J., & Wu, Y. C. (2016). A highly scalable poly-Si junctionless FETs featuring a novel multi-stacking hybrid P/N layer and vertical gate with very high Ion/Ioff for 3D stacked ICs. 於 2016 IEEE Symposium on VLSI Technology, VLSI Technology 2016 [7573429] (Digest of Technical Papers - Symposium on VLSI Technology; 卷 2016-September). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/VLSIT.2016.7573429